library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity remem is
	port(
      Lm_neg, CLK : in std_logic; -- neg significa negado (risco em cima)
      entrada_bw  : in std_logic_vector(3 downto 0);
	   saida_RAM   : out std_logic_vector(3 downto 0):="0000" -- saida para a RAM
	);
end remem;

architecture arquitetura of remem is
begin
	process (CLK,Lm_neg)
   begin
	   if (CLK'event and CLK='1') then
	      if(Lm_neg='0') then
		      saida_RAM<=entrada_bw;
   	   end if;
   	end if;
   end process;
end arquitetura;
